library ieee;
use ieee.std_logic_1164.all;

entity five_or2 is
	port(INA:in std_logic_vector(4 downto 0);
	INB:in std_logic_vector(4 downto 0);
	OUTY:out std_logic_vector(4 downto 0):="00000"
	);
end five_or2;

architecture f_or2 of five_or2 is
begin
	OUTY<=INA or INB;
end f_or2;